x86.lol
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Posts

  • 2025-01-30

    FOSDEM Edition: Thoughts on the Microkernels

  • 2024-09-23

    Hardening C Against ROP: Getting CET Shadow Stacks Working

  • 2024-09-21

    Immutable Systems: Cross-Compiling for RISC-V using Nix Flakes

  • 2024-08-28

    Immutable Systems: NixOS + systemd-repart + systemd-sysupdate

  • 2024-07-07

    Confidential Computing: Complexity vs Security

  • 2023-12-20

    RISC-V: The (Almost) Unused Bit in JALR

  • 2023-11-07

    Split Lock Detection VM Hangs

  • 2023-06-28

    Intel TDX Doesn't Protect You from the Cloud

  • 2023-02-07

    The Flawed Design of Intel TDX

  • 2022-11-26

    Lanzaboote: Towards Secure Boot for NixOS

  • 2022-04-02

    IOAPIC Mysteries: IRQ Pin Assertion Register

  • 2021-11-10

    Intel MPX, CET, SGX, WTF

  • 2020-12-30

    OS Development with RISC-V and ULX3S

  • 2020-10-30

    Complexity in Operating Systems

  • 2020-01-01

    RISC-V Stumbling Blocks

  • 2019-07-04

    1001 Ways of Implementing a System Call

  • 2019-02-12

    Hiding Data in Redundant Instruction Encodings

  • 2019-02-08

    Fingerprinting x86 CPUs using Illegal Opcodes

  • 2019-01-30

    Welcome!

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x86.lol

  • Julian Stecklina
  • js+x86lol@alien8.de
  • blitz
  • blitz
  • blitzclone

I'm blogging about low-level topics and my operating system projects on x86 and RISC-V.